JPH0444417B2 - - Google Patents

Info

Publication number
JPH0444417B2
JPH0444417B2 JP59129288A JP12928884A JPH0444417B2 JP H0444417 B2 JPH0444417 B2 JP H0444417B2 JP 59129288 A JP59129288 A JP 59129288A JP 12928884 A JP12928884 A JP 12928884A JP H0444417 B2 JPH0444417 B2 JP H0444417B2
Authority
JP
Japan
Prior art keywords
frame
lead frame
wire bonding
reversing mechanism
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59129288A
Other languages
English (en)
Japanese (ja)
Other versions
JPS618936A (ja
Inventor
Koji Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP59129288A priority Critical patent/JPS618936A/ja
Publication of JPS618936A publication Critical patent/JPS618936A/ja
Publication of JPH0444417B2 publication Critical patent/JPH0444417B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
JP59129288A 1984-06-25 1984-06-25 半導体装置の製造方法 Granted JPS618936A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59129288A JPS618936A (ja) 1984-06-25 1984-06-25 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59129288A JPS618936A (ja) 1984-06-25 1984-06-25 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS618936A JPS618936A (ja) 1986-01-16
JPH0444417B2 true JPH0444417B2 (en]) 1992-07-21

Family

ID=15005866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59129288A Granted JPS618936A (ja) 1984-06-25 1984-06-25 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS618936A (en])

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH046193Y2 (en]) * 1986-02-28 1992-02-20
JP2537299Y2 (ja) * 1992-02-26 1997-05-28 オーチス エレベータ カンパニー エレベーターの敷居
JP2699753B2 (ja) * 1992-02-28 1998-01-19 株式会社島津製作所 分光光度計

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59101437U (ja) * 1982-12-27 1984-07-09 株式会社松村製作所 リ−ドフレ−ム反転装置

Also Published As

Publication number Publication date
JPS618936A (ja) 1986-01-16

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